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Resolution enhancement technologies are methods used to modify photomasks for integrated circuits (ICs) to compensate for limitations in the lithographic processes used to manufacture the chips. Traditionally, after an IC design has been converted into a physical layout, the timing verified, and the polygons certified to be DRC-clean, the IC was ready for fabrication. The data files representing the various layers were shipped to a mask shop, which used mask-writing equipment to convert each data layer into a corresponding mask, and the masks were shipped to the fab where they were used to repeatedly manufacture the designs in silicon. In the past, the creation of the IC layout was the end of the involvement of electronic design automation. However, as Moore’s law has driven features to ever-smaller dimensions, new physical effects that could be effectively ignored in the past are now having an impact on the features that are formed on the silicon wafer. So even though the final layout may represent what is desired in silicon, the layout can still undergo dramatic alteration through several EDA tools before the masks are fabricated and shipped. These alterations are required not to make any change in the device as designed, but to simply allow the manufacturing equipment, often purchased and optimized for making ICs one or two generations behind, to deliver the new devices. These alterations can be classed as being of two types. The first type is distortion corrections, namely pre-compensating for distortions inherent in the manufacturing process, be it from a processing step, such as: photolithography, etching, planarization, and deposition. These distortions are measured and a suitable model fitted, compensation is carried out usually using a rule or model based algorithm. When applied to printing distortions during photolithography, this distortion compensation is known as Optical Proximity Correction (OPC). The second type of Reticle Enhancement involves actually improving the manufacturability or resolution of the process. Examples of this include: For each of these manufacturability improvement techniques there are certain layouts that either cannot be improved or cause issues in printing. These are classed as non-compliant layouts. These are avoided either at the design stage - using, for instance, Radically Restrictive Design Rules and/or creating addition DRC checks if appropriate. Both the lithographic compensations and manufacturability improvements are usually grouped under the heading resolution enhancement techniques (RET). Such techniques have been used since the 180nm node and have become more aggressively used as minimum feature size as dropped significantly below that of the imaging wavelength, currently limited to 193 nm. This is closely related to, and a part of, the more general category of design for manufacturability (IC) or DFM. After RET, the next step in an EDA flow is usually mask data preparation. == See also == * Resolution enhancement technology 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「resolution enhancement technologies」の詳細全文を読む スポンサード リンク
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